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NXP Semiconductors /LPC43xx /ADCHS /POWER_DOWN

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Interpret as POWER_DOWN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PD_CTRL)PD_CTRL 0RESERVED

Description

Set or clear power down mode

Fields

PD_CTRL

0 = disable power down mode. Register holds value until set by writing 1 to this bit or by descriptor processor when descriptor field POWER_DOWN is set. 1 = enable power down mode. Register holds value until cleared by writing 0 to this bit or by descriptor processor when waking up RECOVERY_TIME before a conversion.
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data